The present invention relates generally to output drivers and in particular the present invention relates to a programmable output driver circuit.
A variety of concepts for digital logic circuits and digital signaling between circuits are known. Early concepts include DTL (Diode-Transistor Logic), TTL (Transistor-Transistor Logic) and ECL (Emitter Coupled Logic). These modes are used within digital logic circuits as well as for digital signaling between circuits or circuit boards.
Concepts designed for transmission of digital data with a high data rate preferably employ differential transmission and reception of digital data, using a pair of signaling wires. Each of these driver circuits only support one mode of operation, such as positive emitter coupled logic (PECL), current mode logic (CML), grounded low voltage differential signal (GLVDS), and low voltage differential signal (LVDS) modes.
Typically, a circuit is designed to operate using one of these data transmission modes. That is, output driver circuits are provided as part of an integrated circuit to communicate with external circuitry. These driver circuits are typically capable of operating in one communication environment only. For example, if a circuit were designed to operate in a PECL mode, it would have to be redesigned to drive data in GLVDS mode.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a driver circuit that can select from numerous possible data communication operating modes. cl SUMMARY OF THE INVENTION
The above-mentioned problems with output drivers and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, an integrated circuit comprises a control circuit to select a data communication mode, and a differential output driver circuit adapted to drive data on first and second external connections based on a selected data communication mode. The selected data communication mode can be selected from the group comprising PECL, LVDS, GLVDS, and CML.
In another embodiment, an output driver circuit comprises a first pull-up transistor coupled in series with a first pull-down transistor between a pull-up bias node and a pull-down bias node. Gates of the first pull-up and first pull-down transistors are coupled to receive a first input data signal, and a common node between the first pull-up and first pull-down transistors is coupled to a first output data node. A second pull-up transistor is coupled in series with a second pull-down transistor between the pull-up bias node and the pull-down bias node. Gates of the second pull-up and second pull-down transistors are coupled to receive a second input data signal, and a common node between the second pull-up and second pull-down transistors is coupled to a second output data node. A control circuit is coupled to provide a pull-up bias current to the pull-up bias node, and provide a pull-down bias current to the pull-down bias node. The bias currents are selected based upon a data communication mode selected from PECL, LVDS, GLVDS, and CML.
A method of outputting data from a output driver circuit is provided. The method comprises selecting a data communication mode from a group comprising PECL, LVDS, GLVDS or CML, and providing bias currents to the output driver circuit based upon the selected data communication mode.